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» Architecture for a Non-deterministic Simulation Machine
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SIAMCOMP
2000
118views more  SIAMCOMP 2000»
15 years 1 months ago
Constructive, Deterministic Implementation of Shared Memory on Meshes
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
HPCA
2003
IEEE
16 years 1 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
15 years 10 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
EVOW
2010
Springer
15 years 8 months ago
Grammatical Evolution Decision Trees for Detecting Gene-Gene Interactions
DEODHAR, SUSHAMNA DEODHAR. Using Grammatical Evolution Decision Trees for Detecting Gene-Gene Interactions in Genetic Epidemiology. (Under the direction of Dr. Alison Motsinger-Re...
Sushamna Deodhar, Alison A. Motsinger-Reif
HPCA
2009
IEEE
15 years 8 months ago
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
Pablo Abad Fidalgo, Valentin Puente, José-&...