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Architecture
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S-Tree: a technique for buffered routing tree synthesis
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Milos Hrkic, John Lillis
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Implementing asynchronous circuits using a conventional EDA tool-flow
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Christos P. Sotiriou
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Timing optimization of FPGA placements by logic replication
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Giancarlo Beraudo, John Lillis
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Interconnect and noise immunity design for the Pentium 4 processor
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Rajesh Kumar 0006
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How to make efficient communication, collaboration, and optimization from system to chip
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Akira Matsuzawa
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