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» Architectures for function evaluation on FPGAs
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133
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DAC
2002
ACM
16 years 4 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
126
Voted
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
16 years 12 days ago
Platform-based resource binding using a distributed register-file microarchitecture
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
Jason Cong, Yiping Fan, Wei Jiang
148
Voted
JUCS
2000
120views more  JUCS 2000»
15 years 3 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
133
Voted
METRICS
2005
IEEE
15 years 9 months ago
Metrics of Software Architecture Changes Based on Structural Distance
Software architecture is an important form of abstraction, representing the overall system structure and the relationship among components. When software is modified from one ver...
Taiga Nakamura, Victor R. Basili
136
Voted
WOSP
2010
ACM
15 years 3 months ago
Automatically improve software architecture models for performance, reliability, and cost using evolutionary algorithms
Quantitative prediction of quality properties (i.e. extrafunctional properties such as performance, reliability, and cost) of software architectures during design supports a syste...
Anne Martens, Heiko Koziolek, Steffen Becker, Ralf...