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113
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ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
15 years 7 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
101
Voted
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 7 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
15 years 7 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
153
Voted
WADS
2009
Springer
291views Algorithms» more  WADS 2009»
15 years 7 months ago
On the Power of the Semi-Separated Pair Decomposition
Abstract. A Semi-Separated Pair Decomposition (SSPD), with parameter s > 1, of a set S ⊂ Rd is a set {(Ai, Bi)} of pairs of subsets of S such that for each i, there are balls ...
Mohammad Ali Abam, Paz Carmi, Mohammad Farshi, Mic...
113
Voted
ARCS
2009
Springer
15 years 7 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
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