125 search results - page 25 / 25 » Area and delay trade-offs in the circuit and architecture de... |
DAC
2004
ACM
14 years 7 months ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
VLSID
2005
IEEE
13 years 11 months ago
2005
IEEE
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...