Sciweavers

125 search results - page 3 / 25
» Area and delay trade-offs in the circuit and architecture de...
Sort
View
DAC
2008
ACM
13 years 8 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
13 years 11 months ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
DAC
2004
ACM
14 years 7 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
FPL
2007
Springer
100views Hardware» more  FPL 2007»
14 years 12 days ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
DAC
2005
ACM
14 years 7 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...