Sciweavers

16 search results - page 3 / 4
» Area efficient DSP datapath synthesis
Sort
View
DAC
2000
ACM
14 years 7 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
SCOPES
2005
Springer
13 years 11 months ago
Software Synthesis from the Dataflow Interchange Format
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...
Chia-Jui Hsu, Shuvra S. Bhattacharyya
16
Voted
ISSS
1996
IEEE
134views Hardware» more  ISSS 1996»
13 years 10 months ago
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
Miguel Miranda, Francky Catthoor, Martin Janssen, ...
IPPS
2002
IEEE
13 years 11 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
DAC
2004
ACM
14 years 7 months ago
Multiple constant multiplication by time-multiplexed mapping of addition chains
An important primitive in the hardware implementations of linear DSP transforms is a circuit that can multiply an input value by one of several different preset constants. We prop...
James C. Hoe, Markus Püschel, Peter Tummeltsh...