70 search results - page 7 / 14 » Arithmetic optimization for custom instruction set synthesis |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
ISSS
1998
IEEE
15 years 1 months ago
1998
IEEE
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
ARC
2008
Springer
14 years 11 months ago
2008
Springer
Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction...
76
Voted
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
95
Voted
ASIAN
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. It is customary to write performance-critical parts of arithmetic functions in assembly: this enables finely-tuned algorithms that use specialized processor instructions....