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» Arithmetic optimization for custom instruction set synthesis
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CODES
2002
IEEE
15 years 2 months ago
Compiler-directed customization of ASIP cores
This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft c...
T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
15 years 4 months ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang
CASES
2007
ACM
15 years 1 months ago
Rethinking custom ISE identification: a new processor-agnostic method
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
Ajay K. Verma, Philip Brisk, Paolo Ienne
PLDI
2005
ACM
15 years 3 months ago
Pin: building customized program analysis tools with dynamic instrumentation
Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we ha...
Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
15 years 3 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski