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82
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ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
15 years 5 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
VVS
1998
IEEE
97views Visualization» more  VVS 1998»
15 years 5 months ago
Volume Animation Using the Skeleton Tree
In this paper, we describe a technique to animate volumes using a volumetric skeleton. The skeleton is computed from the actual volume, based on a reversible thinning procedure us...
Nikhil Gagvani, Deepak R. Kenchammana-Hosekote, De...
PADS
1996
ACM
15 years 4 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...
83
Voted
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
15 years 4 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
IPPS
1994
IEEE
15 years 4 months ago
A Comparison of Heuristics for Scheduling DAGs on Multiprocessors
Many algorithms to schedule DAGs on multiprocessors have been proposed, but there has been little work done to determine their effectiveness. Since multi-processor scheduling is a...
Carolyn McCreary, A. A. Khan, J. J. Thompson, M. E...