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ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
14 years 10 months ago
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Webe...
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
15 years 1 months ago
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
TCC
2007
Springer
91views Cryptology» more  TCC 2007»
15 years 3 months ago
Lower Bounds for Non-interactive Zero-Knowledge
Abstract. We establish new lower bounds and impossibility results for noninteractive zero-knowledge proofs and arguments with set-up assumptions. – For the common random string m...
Hoeteck Wee
SAS
2009
Springer
281views Formal Methods» more  SAS 2009»
15 years 10 months ago
A Verifiable, Control Flow Aware Constraint Analyzer for Bounds Check Elimination
The Java programming language requires that out-of-bounds array accesses produce runtime exceptions. In general, this requires a dynamic bounds check each time an array element is...
David Niedzielski, Jeffery von Ronne, Andreas Gamp...
FOSSACS
2004
Springer
15 years 3 months ago
Probabilistic Bisimulation and Equivalence for Security Analysis of Network Protocols
Abstract. Using a probabilistic polynomial-time process calculus designed for specifying security properties as observational equivalences, we develop a form of bisimulation that j...
Ajith Ramanathan, John C. Mitchell, Andre Scedrov,...