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IPPS
2010
IEEE
15 years 2 months ago
Runtime checking of serializability in software transactional memory
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
Arnab Sinha, Sharad Malik
147
Voted
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 11 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
153
Voted
SC
1992
ACM
15 years 9 months ago
Willow: A Scalable Shared Memory Multiprocessor
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
John K. Bennett, Sandhya Dwarkadas, Jay A. Greenwo...
165
Voted
FPL
2004
Springer
164views Hardware» more  FPL 2004»
15 years 8 months ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
SC
1995
ACM
15 years 8 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...