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» Assessing Architectural Complexity
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ISCAS
2007
IEEE
139views Hardware» more  ISCAS 2007»
15 years 10 months ago
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
ISVC
2007
Springer
15 years 10 months ago
A Control Architecture for Long-Term Autonomy of Robotic Assistants
A major challenge in deploying service robots into the real world is to design a framework that provides effective, long-term interactions with people. This includes interacting w...
Christopher King, Xavier Palathingal, Monica N. Ni...
102
Voted
ECBS
2006
IEEE
90views Hardware» more  ECBS 2006»
15 years 10 months ago
Evaluating Alternatives for Architecture-Oriented Refactoring
Refactoring of software systems represents an fundamental way of improving their quality properties. Large-scale refactoring has to be performed at an architectural level to execu...
Sven Wohlfarth, Matthias Riebisch
DATE
2005
IEEE
165views Hardware» more  DATE 2005»
15 years 9 months ago
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
Francesco Poletti, Antonio Poggiali, Paul Marchal
118
Voted
ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
15 years 9 months ago
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed