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» Assessing Architectural Complexity
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DSD
2008
IEEE
136views Hardware» more  DSD 2008»
15 years 10 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...
SAMT
2007
Springer
138views Multimedia» more  SAMT 2007»
15 years 10 months ago
A Constraint-Based Graph Visualisation Architecture for Mobile Semantic Web Interfaces
Abstract. Multimodal and dialogue-based mobile interfaces to the Semantic Web offer access to complex knowledge and information structures. We explore more fine-grained co-ordina...
Daniel Sonntag, Philipp Heim
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 9 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
JCDL
2004
ACM
89views Education» more  JCDL 2004»
15 years 9 months ago
Machine learning for information architecture in a large governmental website
This paper describes ongoing research into the application of machine learning techniques for improving access to governmental information in complex digital libraries. Under the ...
Miles Efron, Jonathan L. Elsas, Gary Marchionini, ...
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 8 months ago
Detailed routing architectures for embedded programmable logic IP cores
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
Peter Hallschmid, Steven J. E. Wilton