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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
16 years 7 days ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
16 years 7 days ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
ICCCN
2008
IEEE
16 years 1 days ago
A Structured Hardware/Software Architecture for Embedded Sensor Nodes
—Owing to the limited requirement for sensor processing in early networked sensor nodes, embedded software was generally built around the communication stack. Modern sensor nodes...
Geoff V. Merrett, Alex S. Weddell, Nick R. Harris,...
IEEEPACT
2005
IEEE
15 years 11 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
SAC
2004
ACM
15 years 11 months ago
Towards a flexible, process-oriented IT architecture for an integrated healthcare network
Healthcare information systems play an important role in improving healthcare quality. As providing healthcare increasingly changes from isolated treatment episodes towards a cont...
Mario Beyer, Klaus Kuhn, Christian Meiler, Stefan ...