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» Assessing Architectural Complexity
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ASPLOS
2006
ACM
16 years 7 hour ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
INTERSENSE
2006
ACM
15 years 12 months ago
Programming wireless sensor networks with logical neighborhoods
— Wireless sensor network (WSN) architectures often feature a (single) base station in charge of coordinating the application functionality. Although this assumption simplified ...
Luca Mottola, Gian Pietro Picco
CGO
2005
IEEE
15 years 11 months ago
Optimizing Sorting with Genetic Algorithms
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...
Xiaoming Li, María Jesús Garzar&aacu...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 11 months ago
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
ICS
2004
Tsinghua U.
15 years 11 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer