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» Assessing Architectural Complexity
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VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
16 years 5 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
16 years 5 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
VLSID
2002
IEEE
91views VLSI» more  VLSID 2002»
16 years 5 months ago
Rational ABCD Modeling of High-Speed Interconnects
This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-s...
Qinwei Xu, Pinaki Mazumder
HPCA
2006
IEEE
16 years 5 months ago
CORD: cost-effective (and nearly overhead-free) order-recording and data race detection
Chip-multiprocessors are becoming the dominant vehicle for general-purpose processing, and parallel software will be needed to effectively utilize them. This parallel software is ...
Milos Prvulovic
HPCA
2006
IEEE
16 years 5 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...