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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 6 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
HPCA
2003
IEEE
16 years 25 days ago
Variability in Architectural Simulations of Multi-Threaded Workloads
Multi-threaded commercial workloads implement many important internet services. Consequently, these workloads are increasingly used to evaluate the performance of uniprocessor and...
Alaa R. Alameldeen, David A. Wood
ICDCS
2010
IEEE
15 years 20 days ago
Resource Allocation in Distributed Mixed-Criticality Cyber-Physical Systems
—Large-scale distributed cyber-physical systems will have many sensors/actuators (each with local micro-controllers), and a distributed communication/computing backbone with mult...
Karthik Lakshmanan, Dionisio de Niz, Ragunathan Ra...
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DCOSS
2006
Springer
15 years 4 months ago
Distance-Sensitive Information Brokerage in Sensor Networks
In a sensor network information from multiple nodes must usually be aggregated in order to accomplish a certain task. A natural way to view this information gathering is in terms o...
Stefan Funke, Leonidas J. Guibas, An Nguyen, Yusu ...
IEEEPACT
2008
IEEE
15 years 6 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...