914 search results - page 156 / 183 » Assessing the performance limits of parallelized near-thresh... |
110
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HPCA
2003
IEEE
16 years 24 days ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
108
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HPCA
2009
IEEE
16 years 29 days ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
112
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HPCA
2001
IEEE
16 years 24 days ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
78
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ICMCS
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper, a high-level optimization methodology is applied for the implementation of the well-known Convolutional Face Finder (CFF) algorithm for real-time applications on ce...
112
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CC
2006
Springer
15 years 4 months ago
2006
Springer
The polyhedral model is known to be a powerful framework to reason about high level loop transformations. Recent developments in optimizing compilers broke some generally accepted ...