914 search results - page 176 / 183 » Assessing the performance limits of parallelized near-thresh... |
137
Voted
IEEEPACT
2009
IEEE
14 years 11 months ago
2009
IEEE
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
131
Voted
TSE
2012
13 years 4 months ago
2012
— As firms increasingly rely on information systems to perform critical functions the consequences of software defects can be catastrophic. Although the software engineering lite...
125
Voted
SPIN
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. Computational resources are increasing rapidly with the explosion of multi-core processors readily available from major vendors. Model checking needs to harness these res...
114
Voted
HPCA
2009
IEEE
16 years 2 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
120
Voted
HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...