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ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
16 years 1 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
RTAS
2007
IEEE
15 years 11 months ago
Performance Debugging of Real-Time Systems Using Multicriteria Schedulability Analysis
Most of today’s real-time embedded systems consist of a heterogeneous mix of fully-programmable processors, fixed-function components or hardware accelerators, and partially-pr...
Unmesh D. Bordoloi, Samarjit Chakraborty
CODES
2006
IEEE
15 years 11 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
149
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ISCIS
2003
Springer
15 years 10 months ago
Multiple Description Coding for Image Data Hiding in the Spatial Domain
In this paper, we develop a robust image data hiding scheme based on multiple description coding of the signature image. At the transmitter, the signature image is encoded by balan...
Mohsen Ashourian, Yo-Sung Ho