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» Associative Memory in an Immune-Based System
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ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
15 years 7 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
NECO
1998
100views more  NECO 1998»
14 years 9 months ago
Memory Maintenance via Neuronal Regulation
Since their conception half a century ago Hebbian cell assemblies have become a basic term in the Neurosciences, and the idea that learning takes place through synaptic modi catio...
David Horn, Nir Levy, Eytan Ruppin
DAC
1999
ACM
15 years 2 months ago
Exact Memory Size Estimation for Array Computations without Loop Unrolling
This paper presents a new algorithm for exact estimation of the minimum memory size required by programs dealing with array computations. Memory size is an important factor a ecti...
Ying Zhao, Sharad Malik
85
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ICPP
2007
IEEE
15 years 4 months ago
Architectural Challenges in Memory-Intensive, Real-Time Image Forming
The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial quest...
Anders Ahlander, H. Hellsten, K. Lind, J. Lindgren...
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
15 years 4 months ago
Improving memory bank-level parallelism in the presence of prefetching
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N...