65 search results - page 7 / 13 » Asynchronous Data-Driven Circuit Synthesis |
DAC
1999
ACM
15 years 10 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
ASYNC
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
IFIP
1999
Springer
15 years 1 months ago
1999
Springer
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
70
Voted
SBCCI
2006
ACM
15 years 3 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...