27 search results - page 5 / 6 » Asynchronous circuits transient faults sensitivity evaluatio... |
EDCC
1999
Springer
13 years 10 months ago
1999
Springer
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly i...
ICCD
2008
IEEE
14 years 3 months ago
2008
IEEE
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...