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TVLSI
2008
133views more  TVLSI 2008»
14 years 9 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
14 years 9 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
PC
1998
153views Management» more  PC 1998»
14 years 9 months ago
Compilation Techniques for Out-of-Core Parallel Computations
The difficulty of handling out-of-core data limits the performance of supercomputers as well as the potential of the parallel machines. Since writing an efficient out-of-core ve...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
TIT
1998
105views more  TIT 1998»
14 years 9 months ago
Diversity Waveform Sets for Delay-Doppler Imaging
Abstract— Properties of the ambiguity function and the uncertainty relation of Fourier transforms assert fundamental limitations on the ability of any single radar waveform of co...
Jiann-Ching Guey, Mark R. Bell
RSA
2008
81views more  RSA 2008»
14 years 9 months ago
Analyzing linear mergers
Mergers are functions that transform k (possibly dependent) random sources into a single random source, in a way that ensures that if one of the input sources has minentropy rate ...
Zeev Dvir, Ran Raz