94 search results - page 11 / 19 » Automated Analysis of Memory Access Behavior |
104
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TVLSI
2008
14 years 9 months ago
2008
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
105
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
111
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CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
100
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VLDB
1999
ACM
15 years 1 months ago
1999
ACM
As random access memory gets cheaper, it becomes increasingly affordable to build computers with large main memories. We consider decision support workloads within the context of...
72
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DAC
2007
ACM
15 years 10 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...