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ICASSP
2011
IEEE
14 years 7 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan
147
Voted
EDBT
2008
ACM
159views Database» more  EDBT 2008»
16 years 3 months ago
Automaton in or out: run-time plan optimization for XML stream processing
Many systems such as Tukwila and YFilter combine automaton and algebra techniques to process queries over tokenized XML streams. Typically in this architecture, an automaton is fi...
Hong Su, Elke A. Rundensteiner, Murali Mani
124
Voted
ICASSP
2008
IEEE
15 years 10 months ago
Accurate models for estimating area and power of FPGA implementations
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabar...
ERSA
2009
147views Hardware» more  ERSA 2009»
15 years 1 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
163
Voted
ICASSP
2011
IEEE
14 years 7 months ago
Efficient distributed resampling for particle filters
In particle filtering, resampling is the only step that cannot be fully parallelized. Recently, we have proposed algorithms for distributed resampling implemented on architecture...
Balakumar Balasingam, Miodrag Bolic, Petar M. Djur...