Sciweavers

690 search results - page 66 / 138
» Automated Architectural Exploration for Signal Processing Al...
Sort
View
124
Voted
TVLSI
2008
133views more  TVLSI 2008»
15 years 3 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
EJWCN
2011
197views more  EJWCN 2011»
14 years 10 months ago
Comparison among Cognitive Radio Architectures for Spectrum Sensing
Recently, the growing success of new wireless applications and services has led to overcrowded licensed bands, inducing the governmental regulatory agencies to consider more flex...
Luca Bixio, Marina Ottonello, Mirco Raffetto, Carl...
140
Voted
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 9 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
15 years 8 months ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
JEC
2006
61views more  JEC 2006»
15 years 3 months ago
Time-constrained loop scheduling with minimal resources
Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha