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DAC
2009
ACM
15 years 7 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 9 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 8 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
DAC
2009
ACM
16 years 4 months ago
Spectral techniques for high-resolution thermal characterization with limited sensor data
Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated...
Ryan Cochran, Sherief Reda
164
Voted
DAC
2004
ACM
16 years 4 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening