In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal ...
Haoxing Ren, David Zhigang Pan, Charles J. Alpert,...
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...