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ARC
2008
Springer
104views Hardware» more  ARC 2008»
15 years 5 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
158
Voted
ICPP
1999
IEEE
15 years 7 months ago
Coherence-Centric Logging and Recovery for Home-Based Software Distributed Shared Memory
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...
Angkul Kongmunvattana, Nian-Feng Tzeng
119
Voted
CLUSTER
2006
IEEE
15 years 9 months ago
Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
Lei Chai, Albert Hartono, Dhabaleswar K. Panda
144
Voted
PODC
2009
ACM
16 years 20 days ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve
IPPS
1997
IEEE
15 years 7 months ago
Dynamic Processor Scheduling with Client Resources for Fast Multi-Resolution WWW Image Browsing
WWW-based Internet information service has grown enormously during the last few years, and major performance bottlenecks have been caused by WWW server and Internet bandwidth inad...
Daniel Andresen, Tao Yang, David Watson, Athanassi...