Sciweavers

3181 search results - page 502 / 637
» Automated Deployment Support for Parallel Distributed Comput...
Sort
View
ICPP
1996
IEEE
15 years 7 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
ICPP
1993
IEEE
15 years 7 months ago
A Unified Model for Concurrent Debugging
: Events are occurrence instances of actions. The thesis of this paper is that the use of “actions”, instead of events, greatly simplifies the problem of concurrent debugging....
S. I. Hyder, John Werth, James C. Browne
ICPP
1994
IEEE
15 years 7 months ago
Optimizing IPC Performance for Shared-Memory Multiprocessors
We assert that in order to perform well, a shared-memory multiprocessorinter-process communication (IPC)facility mustavoid a) accessing any shared data, and b) acquiring any locks...
Benjamin Gamsa, Orran Krieger, Michael Stumm
ECOOPW
1994
Springer
15 years 7 months ago
Abstracting Interactions Based on Message Sets
ing Interactions Based on Message Sets Svend Frr 1 and Gul Agha2. 1 Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA 94303 2 University of Illinois, 1304 W. Springf...
Svend Frølund, Gul Agha
ICS
1993
Tsinghua U.
15 years 7 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal