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» Automated Design Improvement by Example
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147
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VLSISP
2011
216views Database» more  VLSISP 2011»
14 years 10 months ago
Accurate Area, Time and Power Models for FPGA-Based Implementations
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Cha...
99
Voted
DAC
2009
ACM
16 years 4 months ago
Mode grouping for more effective generalized scheduling of dynamic dataflow applications
For a number of years, dataflow concepts have provided designers of digital signal processing systems with environments capable of expressing high-level software architectures as ...
William Plishker, Nimish Sane, Shuvra S. Bhattacha...
136
Voted
DAC
2004
ACM
16 years 4 months ago
Placement feedback: a concept and method for better min-cut placements
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...
Andrew B. Kahng, Sherief Reda
143
Voted
SAS
1999
Springer
106views Formal Methods» more  SAS 1999»
15 years 8 months ago
Static Analyses for Eliminating Unnecessary Synchronization from Java Programs
This paper presents and evaluates a set of analyses designed to reduce synchronization overhead in Java programs. Monitor-based synchronization in Java often causes significant ove...
Jonathan Aldrich, Craig Chambers, Emin Gün Si...
126
Voted
JCM
2007
115views more  JCM 2007»
15 years 3 months ago
eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions
— Radio Frequency Identification (RFID) technology has a lot of potential to improve visibility across the supply chain and automate the business processes. This paper describes ...
Franco Fummi, Giovanni Perbellini