This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
For a number of years, dataflow concepts have provided designers of digital signal processing systems with environments capable of expressing high-level software architectures as ...
William Plishker, Nimish Sane, Shuvra S. Bhattacha...
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...
This paper presents and evaluates a set of analyses designed to reduce synchronization overhead in Java programs. Monitor-based synchronization in Java often causes significant ove...
— Radio Frequency Identification (RFID) technology has a lot of potential to improve visibility across the supply chain and automate the business processes. This paper describes ...