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DAC
2005
ACM
16 years 4 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
DAC
2006
ACM
16 years 4 months ago
Low-power bus encoding using an adaptive hybrid algorithm
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...
Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru...
DAC
2006
ACM
16 years 4 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
DAC
2006
ACM
16 years 4 months ago
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
CHI
2005
ACM
16 years 4 months ago
Feature congestion: a measure of display clutter
Management of clutter is an important factor in the design of user interfaces and information visualizations, allowing improved usability and aesthetics. However, clutter is not a...
Ruth Rosenholtz, Yuanzhen Li, Jonathan Mansfield, ...