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DAC
2005
ACM
15 years 10 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
82
Voted
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
15 years 10 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
DAC
2002
ACM
15 years 10 months ago
Compiler-directed scratch pad memory hierarchy design and management
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
Mahmut T. Kandemir, Alok N. Choudhary
99
Voted
DAC
2003
ACM
15 years 10 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav
BIRTHDAY
2009
Springer
15 years 4 months ago
Web Service Composition via the Customization of Golog Programs with User Preferences
Abstract. We claim that user preferences are a key component of effective Web service composition, and one that has largely been ignored. In this paper we propose a means of speci...
Shirin Sohrabi, Nataliya Prokoshyna, Sheila A. McI...