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ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
15 years 2 months ago
Multi-level placement with circuit schema based clustering in analog IC layouts
This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of cl...
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Sh...
DAC
2000
ACM
16 years 1 days ago
Closing the gap between ASIC and custom: an ASIC perspective
We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, wi...
David G. Chinnery, Kurt Keutzer
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
15 years 2 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
15 years 4 months ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck
CAV
1994
Springer
111views Hardware» more  CAV 1994»
15 years 3 months ago
Automatic Verification of Timed Circuits
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
Tomas Rokicki, Chris J. Myers