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ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Advanced tools for simulation and design of oscillators/PLLs
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Xiaolue Lai, Jaijeet S. Roychowdhury
DAC
2007
ACM
16 years 3 days ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
DATE
2010
IEEE
129views Hardware» more  DATE 2010»
15 years 4 months ago
Block-level bayesian diagnosis of analogue electronic circuits
—Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue...
Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, Han...
DAC
2000
ACM
15 years 3 months ago
Macro-driven circuit design methodology for high-performance datapaths
Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom st...
Mahadevamurty Nemani, Vivek Tiwari
92
Voted
DAC
2006
ACM
16 years 2 days ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...