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DAC
2007
ACM
16 years 3 days ago
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
Kiran Puttaswamy, Gabriel H. Loh
82
Voted
AAAI
2008
15 years 1 months ago
Generating Application-Specific Benchmark Models for Complex Systems
Automated generators for synthetic models and data can play a crucial role in designing new algorithms/modelframeworks, given the sparsity of benchmark models for empirical analys...
Jun Wang, Gregory M. Provan
DAC
2002
ACM
16 years 2 days ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
56
Voted
DAC
2008
ACM
16 years 3 days ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
DAC
2004
ACM
16 years 2 days ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh