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ISLPED
1999
ACM
236views Hardware» more  ISLPED 1999»
15 years 3 months ago
Modeling and automating selection of guarding techniques for datapath elements
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
William E. Dougherty, Donald E. Thomas
DAC
1999
ACM
16 years 3 days ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
15 years 5 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
DAC
2006
ACM
16 years 3 days ago
Circuit simulation based obstacle-aware Steiner routing
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing t...
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
CAV
2008
Springer
131views Hardware» more  CAV 2008»
15 years 1 months ago
Validating High-Level Synthesis
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta