471 search results - page 70 / 95 » Automated Design of Misaligned-Carbon-Nanotube-Immune Circui... |
DAC
2002
ACM
16 years 3 days ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
DAC
2003
ACM
16 years 3 days ago
2003
ACM
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
DAC
2004
ACM
16 years 3 days ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
DAC
2004
ACM
16 years 3 days ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
DAC
2005
ACM
16 years 3 days ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...