471 search results - page 76 / 95 » Automated Design of Misaligned-Carbon-Nanotube-Immune Circui... |
99
Voted
DAC
2004
ACM
16 years 2 days ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
69
Voted
DAC
2006
ACM
16 years 2 days ago
2006
ACM
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
DAC
2009
ACM
16 years 3 days ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
DAC
2006
ACM
16 years 2 days ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
72
Voted
DAC
2009
ACM
16 years 3 days ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...