In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycleaccurate tracing is large and the trace cycle is shallow u...
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...