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ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 6 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
CONCUR
2006
Springer
15 years 5 months ago
A Livelock Freedom Analysis for Infinite State Asynchronous Reactive Systems
We describe an incomplete but sound and efficient livelock freedom test for infinite state asynchronous reactive systems. The method s a system into a set of simple control flow cy...
Stefan Leue, Alin Stefanescu, Wei Wei
IJSEKE
2011
165views more  IJSEKE 2011»
14 years 5 months ago
Model Checking for Verification of Mandatory Access Control Models and Properties
rather wide gap in abstraction between policies and mechanisms. In this paper, we propose a general approach for property verification for MAC models. The approach defines a stan...
Vincent C. Hu, D. Richard Kuhn, Tao Xie, JeeHyun H...
167
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PLDI
2011
ACM
14 years 4 months ago
Finding and understanding bugs in C compilers
Compilers should be correct. To improve the quality of C compilers, we created Csmith, a randomized test-case generation tool, and spent three years using it to find compiler bug...
Xuejun Yang, Yang Chen, Eric Eide, John Regehr
DAC
2002
ACM
16 years 2 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...