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» Automated Logical Verification Based on Trace Abstractions
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ACSD
2004
IEEE
90views Hardware» more  ACSD 2004»
15 years 3 months ago
A Front-End Tool for Automated Abstraction and Modular Verification of Actor-Based Models
Marjan Sirjani, Amin Shali, Mohammad Mahdi Jaghoor...
IJCAI
2003
15 years 1 months ago
Automated Verification: Graphs, Logic, and Automata
Automated verification is one of the most success­ ful applications of automated reasoning in com­ puter science. In automated verification one uses algorithmic techniques to es...
Moshe Y. Vardi
73
Voted
DAC
2003
ACM
16 years 19 days ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
DAC
2007
ACM
16 years 20 days ago
An Effective Guidance Strategy for Abstraction-Guided Simulation
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
Flavio M. de Paula, Alan J. Hu
76
Voted
CADE
2007
Springer
15 years 12 months ago
KeY-C: A Tool for Verification of C Programs
Abstract. We present KeY-C, a tool for deductive verification of C programs. KeY-C allows to prove partial correctness of C programs relative to pre- and postconditions. It is base...
Daniel Larsson, Oleg Mürk, Reiner Hähnle