119 search results - page 6 / 24 » Automated Modeling of Custom Digital Circuits for Test |
DFT
2004
IEEE
15 years 3 months ago
2004
IEEE
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
DAC
2002
ACM
16 years 9 days ago
2002
ACM
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
ITC
2003
IEEE
15 years 4 months ago
2003
IEEE
We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes....
IRI
2007
IEEE
15 years 5 months ago
2007
IEEE
The paper presents a technique for the design of digital systems on the basis of reusable hardware templates, which are circuits with modifiable functionality that might be custom...
DAC
2009
ACM
16 years 10 days ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...