Sciweavers

338 search results - page 31 / 68
» Automated Performance Prediction of Message-Passing Parallel...
Sort
View
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
15 years 8 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
TSMC
1998
62views more  TSMC 1998»
15 years 1 months ago
Performance based design of high-level language-directed computer architectures
— This paper is concerned with the analytical modeling of computer architectures to aid in the design of high-level language-directed computer architectures. High-level language-...
Rajendra S. Katti, Mark L. Manwaring
IPPS
2005
IEEE
15 years 7 months ago
Automated Analysis of Memory Access Behavior
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
Michael Gerndt, Tianchao Li
CNHPCA
2009
Springer
15 years 4 months ago
Parallel Branch Prediction on GPU Platform
Abstract. Branch Prediction is a common function in nowadays microprocessor. Branch predictor is duplicated into multiple copies in each core of a multicore and many-core processor...
Liqiang He, Guangyong Zhang
MICRO
2002
IEEE
159views Hardware» more  MICRO 2002»
15 years 6 months ago
Master/slave speculative parallelization
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution ...
Craig B. Zilles, Gurindar S. Sohi