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DAC
2001
ACM
15 years 10 months ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles
91
Voted
NDSS
2008
IEEE
15 years 3 months ago
Automated Whitebox Fuzz Testing
Fuzz testing is an effective technique for finding security vulnerabilities in software. Traditionally, fuzz testing tools apply random mutations to well-formed inputs of a progr...
Patrice Godefroid, Michael Y. Levin, David A. Moln...
TASE
2008
IEEE
14 years 9 months ago
Modeling and Supervisory Control of Railway Networks Using Petri Nets
In this paper we deal with the problem of modeling railway networks with Petri nets so as to apply the theory of supervisory control for discrete event systems to automatically de...
Alessandro Giua, Carla Seatzu
JSA
1998
72views more  JSA 1998»
14 years 9 months ago
Network conscious design of distributed real-time systems
In this paper, we present a network conscious approach to designing distributed real-time systems. Given a task graph design of the system, the end-to-end constraints on the input...
Jung Woo Park, Young Shin Kim, Seongsoo Hong, Mana...
TOG
2010
157views more  TOG 2010»
14 years 4 months ago
Computer-generated residential building layouts
We present a method for automated generation of building layouts for computer graphics applications. Our approach is motivated by the layout design process developed in architectu...
Paul Merrell, Eric Schkufza, Vladlen Koltun