4359 search results - page 37 / 872 » Automated Pipeline Design |
142
Voted
GLVLSI
2003
IEEE
15 years 10 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
146
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FCCM
1998
IEEE
15 years 9 months ago
1998
IEEE
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
147
Voted
DAC
1992
ACM
15 years 9 months ago
1992
ACM
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
165
Voted
EMSOFT
2004
Springer
15 years 10 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
127
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MTV
2007
IEEE
15 years 11 months ago
2007
IEEE
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...