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ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
15 years 9 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
15 years 9 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
CODES
1998
IEEE
15 years 9 months ago
The construction of a retargetable simulator for an architecture template
Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, v...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
158
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SAS
1999
Springer
106views Formal Methods» more  SAS 1999»
15 years 9 months ago
Static Analyses for Eliminating Unnecessary Synchronization from Java Programs
This paper presents and evaluates a set of analyses designed to reduce synchronization overhead in Java programs. Monitor-based synchronization in Java often causes significant ove...
Jonathan Aldrich, Craig Chambers, Emin Gün Si...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 9 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar