4359 search results - page 714 / 872 » Automated Pipeline Design |
122
click to vote
DAC
2000
ACM
15 years 11 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...